Semiconductor production is becoming less centralized as new foundries are being established across the globe. Some effects of the establishment of new foundries include increasing variation in fabrication processes, voltages, and tolerances (PVT) between different foundries, as well as the chip level. Moreover, as the degree of miniaturization, hybridization, and gate count increases, and greater numbers of smaller transistors associated with diverse functions are integrated to increase performance, many sub-circuits are increasingly controlled by different supply voltages and at different frequencies. This results in performance variations chip-to-chip.
The performance variations can be due to global variations in the fabrication process (i.e., large-scale variations) and/or local variations in the fabrication process (i.e., small-scale variations). As an example of a global variation, an in circuit fabricated by one foundry performs differently than the same type of integrated circuit that has been fabricated at a different foundry. As an example of a local variation, two transistors on the same die, having ideally identical dimensions, can perform differently due to variations in doping. The performance variations can affect yield.
In addition to PVT-based performance variations, in conventional devices, a p-type semiconductor device has less current drive due to reduced charge carrier mobility when compared to an n-type semiconductor, given the existing process and the same physical size. In a complementary logic circuit having p-type and n-type semiconductor devices, the reduced charge carrier mobility can result in an asymmetrical output waveform. A common design technique to mitigate this effect is to design the p-type semiconductor device so that the p-type semiconductor device is larger than the associated n-type semiconductor device. The larger p-type semiconductor device requires circuit area.
In the complementary logic circuit, the output waveforms peak-to-peak voltage can also be affected by electrostatic discharge (ESD) components coupled between the complementary logic circuit's power supplies and the complementary logic circuit. Also, the ESD components require circuit area that could be put to a different use.
Further, in conventional complementary logic circuit circuits, rail-to-rail rise time and fall time varies dependent on output current, output impedance, and input/output loading. For example, resistive, inductive, and capacitive input loading can also affect rail-to-rail rise time and fall time, even given the same output loading.
There are long-felt industry needs for self-correcting circuits such as inverters, buffers, level-shifters, oscillators, and the like that mitigate the effects of performance variations. Further, there are long-felt industry needs for complementary logic circuits that, compared to conventional devices, occupy less layout area on an integrated circuit die, have lower power consumption, and have greater timing accuracy. Thus, there are needs to improve upon classic circuit designs and methods.